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spelling: cacheable

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Signed-off-by: Josh Soref <2119212+jsoref@users.noreply.github.com>
This commit is contained in:
Josh Soref
2025-01-28 14:36:43 -05:00
parent 5489a4c0d3
commit 71513f263b
4 changed files with 10 additions and 10 deletions
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4
src/fw/drivers/mpu.c
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@@ -209,11 +209,11 @@ void mpu_set_task_configurable_regions(MemoryRegion_t *memory_regions,
}
bool mpu_memory_is_cachable(const void *addr) {
bool mpu_memory_is_cacheable(const void *addr) {
if (!dcache_is_enabled()) {
return false;
}
// TODO PBL-37601: We're assuming only SRAM is cachable for now for simplicity sake. We should
// TODO PBL-37601: We're assuming only SRAM is cacheable for now for simplicity sake. We should
// account for MPU configuration and also the fact that memory-mapped QSPI access goes through the
// cache.
return ((uint32_t)addr >= SRAM_BASE) && ((uint32_t)addr < SRAM_END);